The present invention relates generally to continuity testing of electronic devices, and more particularly to a method for diagnosing open defects on non-contacted nodes of an electronic device from measurements obtained from nodes of the electronic device that are capacitively coupled to the non-contacted nodes.
Integrated circuit assemblies are ubiquitous in modern electronic devices, and a large portion of the industrial sector is devoted to the design and manufacture of such devices. As electronic devices are continually being improved and becoming more sophisticated, so are consumers' expectations for the level of quality of these products. Accordingly, new and improved testing techniques are continuously being sought by manufacturers to test the quality of integrated circuits, printed circuit boards, and integrated circuit assemblies after manufacture and prior to shipment of these devices. While testing entails checking many aspects of the product, such as functionality testing and burn-in testing, one of the most important tests after manufacture is basic continuity testing—that is, testing to ensure that all connections that are supposed to be connected between components of the device (e.g., integrated circuit pins to printed circuit boards, integrated circuit lead wires to pins, traces connections between printed circuit board nodes, etc.) are intact.
One common defect often uncovered during continuity testing is known as an “open” defect. In an open defect, an electrical connection is missing between two points in the circuit where electrical continuity should exist. Open defects typically result from problems in the manufacturing process, such as missing solder due to uneven application of solder paste, the unintentional introduction of particles in the wetting process, etc. Thus, during continuity testing of integrated circuit assemblies, connection defects such as open solder joints are diagnosed.
Detection of open defects is often performed using well-known capacitive lead-frame sensing technologies. For example, U.S. Pat. No. 5,557,209 to Crook et al, U.S. Pat. No. 5,420,500 to Kerschner, and U.S. Pat. No. 5,498,964 to Kerschner et al., all of which are hereby incorporated by reference for all that they teach, describe techniques for detecting opens between integrated circuit signal pins and the mounting substrate (typically a printed circuit board). FIG. 1A shows the basic setup and FIG. 1B shows the equivalent circuit model of capacitive lead-frame testing for open signal pins on an integrated circuit.
As shown, an integrated circuit (IC) die 18 is packaged in an IC package 12. The package 12 includes a lead frame 14 supporting a plurality of pins 10a, 10b. Pads of the IC die 18 are connected to the package pins 10a, 10b at the lead frame 14 via bond wires 16a, 16b. The pins 10a, 10b are supposed to be conductively attached, for example by way of solder joints, to pads 8a, 8b of a printed circuit board (PCB) 6. The test setup shown in FIG. 1A determines whether package pins are properly connected to the board at the solder joints. The test setup includes an alternating current (AC) source 2 that applies an AC signal, through a test probe 4a, to a node connected to the pad 8a on the PCB 6 to which a pin under test 10a should be electrically connected. In a typical test environment, the AC signal is typically ten kilohertz (10 kHz) at 0.2 volts. A capacitive sensing probe 20 comprising a conductive sense plate 22 and amplifying buffer 24 is placed on top of the integrated circuit package 12. The capacitive sensing probe 20 is connected to a current measuring device 26, such as an ammeter. Another pin 10b of the integrated circuit 12 is connected to a circuit ground via a grounded probe 4b. 
When the test is performed, the AC signal applied to pad 8a appears on the pin 10a of the integrated circuit package 12. Through capacitive coupling, in particular a capacitance Csense formed between the lead frame 14 and sense plate 22, a current Is is passed to the sense plate 22 and then through the amplifying buffer 24 to the current measuring device 26. If the measured current Is falls between predetermined limits, then the pin 10a is properly connected to the pad 8a. If the pin 10a is not connected to the pad 8a, a capacitance Copen is formed between the pad 8a and pin 10a, altering the current Is measured by the current measuring device 26 such that the measured current Is falls outside the predetermined limits, thereby indicating that an open defect is present at the pin connection.
U.S. patent application Ser. No. 10/703,944 to Parker at al., entitled “Methods And Apparatus For Testing And Diagnosing Open Connections For Sockets And Connectors On Printed Circuit Boards”, hereby incorporated by reference for all that it teaches, extends the capacitive leadframe testing concept to allow the testing of large sockets and connectors, especially when they contain large numbers of pins that are connected to ground and power planes, in particular, this technology creates a “Matched Capacitor Array” (“MCA”) device 30, shown in FIG. 2A, that fits into a connector 40 to be tested. The MCA device 30 includes a plurality of pins 31a–31l that contact corresponding respective sockets 41a–41l of the connector 40. The sockets 41a–41l are supposed to be connected to pads 51a–51l of a PCB via joints 52a–52l, represented also as balls A–L, and it is typically the integrity of these joints 52a–52l that is being tested. Each pin 31a–31l has a tiny, engineered capacitance (C) 33a–33l to a common sense plate 34 (surrounded by a Faraday shield 35) that is then fed to a current measuring device 54 (FIG. 2B). The signal pins 33a, 31c, 31e, 31g, 31i, 31k are paired by an engineered pairing capacitance 32a, 32b, 32c, 32d, 32e, 32f to a respective neighboring power or ground pin 31b, 31d, 31f, 31h, 31j, 31l as shown in FIG. 2A.
The equivalent circuit for this configuration is shown for a capacitively coupled pair of pins 31a and 31b in FIG. 2B. In the illustrative example, the pair-coupling capacitance 32a has been set to 10*C. An AC source generator 52 applies an AC signal to the node 51a on the board to which the socket 41a should be connected. Current transferred to the common sense plate 34 of the MCA 30 is sensed by capacitive sensing probe 38 (FIG. 2A), which grounds the shield 35 via ground channel 37a, 37b. Sensed current on the common sense plate 34 is transferred to the current measuring device 54 over signal channel 38a, 38b. The input to the current measuring device 54 is a virtual ground. The sensed current is proportional to capacitance.
When no opens are present, the signal from signal generator 52 enters joint 52a (ball A). (Note the source impedance is small.) A voltage is developed at joint 52a (ball A). Joint 52b (ball B) is grounded, so the potential across joint 52b (ball B) is zero volts. Thus no current can flow from joint 52b (ball B) to the current meter 54. The value of capacitance measured is C.
If only joint 52a (ball A) is open, no signal will make it to the current meter 54, so the value measured is zero volts.
If only joint 52b (ball B) is open, the grounding of joint 52b (ball B) is prevented. Because the pair-coupling capacitor is much larger (10×) than C, the effective capacitive coupling to the current meter 54 is almost equal to C, resulting in an effective capacitance at the meter of approximately 2*C.
If both joints 52a and 52b (balls A and B) are open, the open on joint 52a (ball A) dominates the result, for a measurement of zero volts. TABLE 1 summarizes the measurement results:
TABLE 1DefectMeasured capacitanceNoneCBall A open0Ball B open2*CBall A and B open0
In this example, the capacitance measurements are differentiated by at least a value of C. As long as the current meter 54 is sensitive over a range of 0 to 2*C, open defects are detectable and can be diagnosed.
The well-known capacitive lead-frame sensing technology mentioned above has for years used the information from TABLE 1 to detect open connections on nodes. A low capacitive measurement indicates that the contacted joint 52a connection at ball A is open. However, previously, no test technique determined open connections on the grounded joint 52b at ball B. Furthermore, no prior art test technique detects opens on node B without actually contacting node B. However, in many electronic devices, not all nodes are accessible for testing. Accordingly, it would be desirable to develop a testing technique for diagnosing open defects on inaccessible or non-contacted nodes of an electronic device.